%0 Journal Article %A Olivito, Javier %A Serrano, Felipe %A Clemente Barreira, Juan Antonio %A Mecha, Hortensia %A Resano, Javier %T Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 FPGA %D 2018 %@ 1751-8601 %U https://hdl.handle.net/20.500.14352/11976 %X In this paper we have evaluated the overhead and the tradeoffs of a set of components usually included in a system with run-time partial reconfiguration implemented on a Xilinx Virtex-5. Our analysis shows the benefits of including a scratchpad memory inside the reconfiguration controller in order to improve the efficiency of the reconfiguration process. We have designed a simple controller for this scratchpad that includes support for prefetching and caching in order to further reduce both the energy and latency overhead. %~