RT Journal Article
T1 Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 FPGA
A1 Olivito, Javier
A1 Serrano, Felipe
A1 Clemente Barreira, Juan Antonio
A1 Mecha, Hortensia
A1 Resano, Javier
AB In this paper we have evaluated the overhead and the tradeoffs of a set of components usually included in a system with run-time partial reconfiguration implemented on a Xilinx Virtex-5. Our analysis shows the benefits of including a scratchpad memory inside the reconfiguration controller in order to improve the efficiency of the reconfiguration process. We have designed a simple controller for this scratchpad that includes support for prefetching and caching in order to further reduce both the energy and latency overhead.
PB Institution of Engineering and Technology
SN 1751-8601
YR 2018
FD 2018-01-16
LK https://hdl.handle.net/20.500.14352/11976
UL https://hdl.handle.net/20.500.14352/11976
LA eng
NO Ministerio de Economía y Competitividad (MINECO)
NO Gobierno de Aragón
DS Docta Complutense
RD 30 abr 2024