TY  - JOUR
AU  - Olivito, Javier
AU  - Serrano, Felipe
AU  - Clemente Barreira, Juan Antonio
AU  - Mecha, Hortensia
AU  - Resano, Javier
PY  - 2018
DO  - 10.1049/iet-cdt.2016.0095
SN  - 1751-8601
UR  - https://hdl.handle.net/20.500.14352/11976
T2  - IET Computers & Digital Techniques
AB  - In this paper we have evaluated the overhead and the tradeoffs of a set of components usually included in a system with run-time partial reconfiguration implemented on a Xilinx Virtex-5. Our analysis shows the benefits of including a scratchpad memory...
LA  - eng
M2  - 1
PB  - Institution of Engineering and Technology
TI  - Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 FPGA
TY  - journal article
ER  -