RT Book, Section
T1 2-D wavelet transform enhancement on general-purpose microprocessors: memory hierarchy and SIMD parallelism exploitation
A1 Chaver Martínez, Daniel Ángel
A1 Tenllado Van Der Reijden, Christian Tomás
A1 Piñuel Moreno, Luis
A1 Prieto Matías, Manuel
A1 Tirado Fernández, José Francisco
AB This paper addresses the implementation of a 2-D Discrete Wavelet Transform on general-purpose microprocessors, focusing on both memory hierarchy and SIMD parallelization issues. Both topics are somewhat related, since SIMD extensions are only useful if the memory hierarchy is efficiently exploited. In this work, locality has been significantly improved by means of a novel approach called pipelined computation, which complements previous techniques based on loop tiling and non-linear layouts. As experimental platforms we have employed a Pentium-III (P-III) and a Pentium-4 (P-4) microprocessor. However, our SIMD-oriented tuning has been exclusively performed at source code level. Basically, we have reordered some loops and introduced some modifications that allow automatic vectorization. Taking into account the abstraction level at which the optimizations are carried out, the speedups obtained on the investigated platforms are quite satisfactory, even though further improvement can be obtained by dropping the level of abstraction (compiler intrinsics or assembly code).
PB Springer-Verlag Berlin
SN 3-540-00303-7
YR 2002
FD 2002
LK https://hdl.handle.net/20.500.14352/60901
UL https://hdl.handle.net/20.500.14352/60901
LA eng
NO International Conference on High Performance Computing (HiPC 2002) (9th . Dec 18-21, 2002. Bangalore, India).
DS Docta Complutense
RD 17 abr 2025