RT Journal Article
T1 Revisiting Conventional Task Schedulers to Exploit Asymmetry in ARM big.LITTLE Architectures for Dense Linear Algebra
A1 Costero Valero, Luis María
A1 Igual Peña, Francisco Daniel
A1 Olcoz Herrero, Katzalin
A1 Catalán Pallarés, Sandra
A1 Rodríguez Sánchez, Rafael
A1 Quintana-Ortí, Enrique S.
AB Dealing with asymmetry in the architecture opens a plethora of questions related with the performance- and energy-efficient scheduling of task-parallel applications. While there exist early attempts to tackle this problem, for example via ad-hoc strategies embedded in a runtime framework, in this paper we take a different path, which consists in addressing the asymmetry at the library-level by developing a few asymmetry-aware fundamental kernels. The appealing consequence is that the architecture heterogeneity remains then hidden from the task scheduler.In order to illustrate the advantage of our approach, we employ two well-known matrix factorizations, key to the solution of dense linear systems of equations. From the perspective of the architecture, we consider two low-power processors, one of them equipped with ARM big.LITTLE technology; furthermore, we include in the study a different scenario, in which the asymmetry arises when the cores of an Intel Xeon server operate at two distinct frequencies. For the specific domain of dense linear algebra, we show that dealing with asymmetry at the library-level is not only possible but delivers higher performance than a naive approach based on an asymmetry-oblivious scheduler. Furthermore, this solution is also competitive in terms of performance compared with an ad-hoc asymmetry-aware scheduler furnished with sophisticated scheduling techniques.
PB Elsevier
SN 0167-8191
YR 2017
FD 2017-06-01
LK https://hdl.handle.net/20.500.14352/96504
UL https://hdl.handle.net/20.500.14352/96504
LA eng
DS Docta Complutense
RD 6 oct 2024