RT Conference Proceedings
T1 Customized Nios II multi-cycle instructions to accelerate block-matching techniques
A1 González, Diego
A1 Botella Juan, Guillermo
A1 García Sánchez, Carlos
A1 Meyer Bäse, Anke
A1 Meyer Bäse, Uwe
A1 Prieto Matías, Manuel
AB This study focuses on accelerating the optimization of motion estimation algorithms, which are widely used in video coding standards, by using both the paradigm based on Altera Custom Instructions as well as the efficient combination of SDRAM and On-Chip memory of Nios II processor. Firstly, a complete code profiling is carried out before the optimization in order to detect time leaking affecting the motion compensation algorithms. Then, a multi-cycle Custom Instruction which will be added to the specific embedded design is implemented. The approach deployed is based on optimizing SOC performance by using an efficient combination of On-Chip memory and SDRAM with regards to the reset vector, exception vector, stack, heap, read/write data (.rwdata), read only data (.rodata), and program text (.text) in the design. Furthermore, this approach aims to enhance the said algorithms by incorporating Custom Instructions in the Nios II ISA. Finally, the efficient combination of both methods is then developed to build the final embedded system. The present contribution thus facilitates motion coding for low-cost Soft-Core microprocessors, particularly the RISC architecture of Nios II implemented in FPGA. It enables us to construct an SOC which processes 50×50 @ 180 fps.
PB SPIE
YR 2015
FD 2015-02-27
LK https://hdl.handle.net/20.500.14352/24977
UL https://hdl.handle.net/20.500.14352/24977
LA eng
DS Docta Complutense
RD 27 sept 2024