RT Conference Proceedings
T1 Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks
A1 Komalan, Manu
A1 Rock, Oh Hyung
A1 Hartmann, Matthias
A1 Sakhare, Sushi
A1 Tenllado Van Der Reijden, Christian Tomás
A1 Gómez, José Ignacion
A1 Kar, Gouri
A1 Furnemont, Arnaud
A1 Catthoor, Francky
A1 Senni, Sophiane
A1 Novo, David
A1 Gamatie, Abdoulaye
A1 Torres, Lionel
AB Current main memory organizations in embedded and mobile application systems are DRAM dominated. The ever-increasing gap between today's processor and memory speeds makes the DRAM subsystem design a major aspect of computer system design. However, the limitations to DRAM scaling and other challenges like refresh provide undesired trade-offs between performance, energy and area to be made by architecture designers. Several emerging NVM options are being explored to at least partly remedy this but today it is very hard to assess the viability of these proposals because the simulations are not fully based on realistic assumptions on the NVM memory technologies and on the system architecture level. In this paper, we propose to use realistic, calibrated STT-MRAM models and a well calibrated cross-layer simulation and exploration framework, named SEAT, to better consider technologies aspects and architecture constraints. We will focus on general purpose/mobile SoC multi-core architectures. We will highlight results for a number of relevant benchmarks, representatives of numerous applications based on actual system architecture. The most energy efficient STT-MRAM based main memory proposal provides an average energy consumption reduction of 27% at the cost of 2x the area and the least energy efficient STT-MRAM based main memory proposal provides an average energy consumption reduction of 8% at the around the same area or lesser when compared to DRAM.
SN 1558-1101
YR 2018
FD 2018
LK https://hdl.handle.net/20.500.14352/97828
UL https://hdl.handle.net/20.500.14352/97828
LA eng
NO M. Komalan et al., "Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks," 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, 2018, pp. 103-108.
NO Ministerio de Ciencia e Innovación (España)
DS Docta Complutense
RD 20 abr 2025