RT Journal Article
T1 Comparative study of meta-heuristic 3D floorplanning algorithms
A1 Cuesta-Infante, Alfredo
A1 Colmenar, J. Manuel
A1 Bankovic, Zorana
A1 Zapater, Marina
A1 Hidalgo, J. Ignacio
A1 Moya, José M.
A1 Risco Martín, José Luis
A1 Ayala Rodrigo, José Luis
AB Constant necessity of improving performance has brought the invention of 3D chips. The improvement is achieved due to the reduction of wire length, which results in decreased nterconnection delay. However, 3D stacks have less heat dissipation due to the inner layers, which leads to increased temperature and the appearance of hot spots. This problem can be mitigated through appropriate floorplanning. For this reason, in this work we present and compare five different solutions for floorplanning of 3D chips. Each solution uses a different representation, and all are based on meta-heuristic algorithms, namely three of them are based on simulated annealing, while two other are based on evolutionary algorithms. The results show great capability of all the solutions in optimizing temperature and wire length, as they all exhibit significant improvements comparing to the benchmark floorplans.
YR 2015
FD 2015
LK https://hdl.handle.net/20.500.14352/113289
UL https://hdl.handle.net/20.500.14352/113289
LA eng
DS Docta Complutense
RD 10 abr 2025