TY  - JOUR
AU  - Serrano, Felipe
AU  - Clemente Barreira, Juan Antonio
AU  - Mecha López, Hortensia
PY  - 2015
DO  - 10.1109/TNS.2015.2447391
SN  - 0018-9499
UR  - https://hdl.handle.net/20.500.14352/24600
T2  - IEEE Transactions on Nuclear Science
AB  - This paper presents a methodology to emulate Single Event Upsets (SEUs) in FPGA flip-flops (FFs). Since the content of a FF is not modifiable through the FPGA configuration memory bits, a dedicated design is required for fault injection in the FFs....
LA  - eng
M2  - 1617
PB  - IEEE
KW  - Single event upset (SEU)
KW  - Fault injection
KW  - Flip-flops
KW  - FPGA
KW  - Reliability
TI  - A Methodology to Emulate Single Event Upsets in Flip-Flops using FPGAs through Partial Reconfiguration and Instrumentation
TY  - journal article
VL  - 62
ER  -