RT Journal Article
T1 Reliability and Makespan Optimization of Hardware Task Graphs in Partially Reconfigurable Platforms
A1 Ramezani, Reza
A1 Sedaghat, Yasser
A1 Naghibzadeh, Mahmoud
A1 Clemente, Juan Antonio
AB This paper addresses the problem of reliability and makespan optimization of hardware task graphs in reconfigurable platforms by applying fault tolerance (FT) techniques to the running tasks based on the exploration of the Pareto set of solutions. In the presented solution, in contrast to the existing approaches in the literature, task graph scheduling, tasks parallelism, reconfiguration delay, and FT requirements are taken into account altogether. This paper first presents a model for hardware task graphs, task prefetch and scheduling, reconfigurable computer, and a fault model for reliability. Then, a mathematical model of an integer nonlinear multi-objective optimization problem is presented for improving the FT of hardware task graphs, scheduled in partially reconfigurable platforms. Experimental results show the positive impacts of choosing the FT techniques selected by the proposed solution, which is named Pareto-based. Thus, in comparison to nonfault-tolerant designs or other state-of-the-art FT approaches, without increasing makespan, about 850% mean time to failure (MTTF) improvement is achieved and, without degrading reliability, makespan is improved by 25%. In addition, experiments in fault-varying environments have demonstrated that the presented approach outperforms the existing state-of-the-art adaptive FT techniques in terms of both MTTF and makespan.
PB The Institute of Electrical and Electronics Engineers (IEEE)
SN 0018-9251
YR 2017
FD 2017-04
LK https://hdl.handle.net/20.500.14352/18074
UL https://hdl.handle.net/20.500.14352/18074
LA eng
NO Ministerio de Ciencia e Innovación (MICINN)
NO Ministry of Science, Research and Technology of Iran
DS Docta Complutense
RD 9 abr 2025