RT Book, Section
T1 Reconfigurable implementation of GF(2^m) bit-parallel multipliers
A1 Imaña Pascual, José Luis
AB Hardware implementations of arithmetic operations over binary finite fields GF(2^m) are widely used in several important applications, such as cryptography, digital signal processing and error-control codes. In this paper, efficient. reconfigurable implementations of bit-parallel canonical basis multipliers over binary fields generated by type II irreducible pentanomials f_(y) = y^m + y^(n+2) + y^(n+1) + y^n + 1 are presented. These pentanomials are important because all five binary fields recommended by NIST for ECDSA can be constructed using such polynomials. In this work, a new approach for CF(2^m) multiplication based on type II pentanomials is given and several post-place and route implementation results in Xilinx Artix-7 FPGA are reported. Experimental results show that the proposed multiplier implementations improve the area x time parameter when compared with similar multipliers found in the literature.
PB IEEE
SN 978-3-9819-2630-9
YR 2018
FD 2018-04-23
LK https://hdl.handle.net/20.500.14352/13994
UL https://hdl.handle.net/20.500.14352/13994
LA eng
NO © 2018 IEEE ISSN 1558-1101Design, Automation and Test in Europe Conference and Exhibition (DATE) (2018. Dresde, Alemania)Issn: 1530-1591This work has been supported by the EU (FEDER) and the Spanish MINECO, under grants TIN 2015-65277-R and TIN2012-32180.
NO Ministerio de Economía y Competitividad (MINECO)/FEDER
DS Docta Complutense
RD 5 abr 2025