RT Journal Article
T1 Single Event Upsets under 14-MeV Neutrons in a 28-nm SRAM-based FPGA in Static Mode
A1 Fabero Jiménez, Juan Carlos
A1 Mecha López, Hortensia
A1 Franco Peláez, Francisco Javier
A1 Clemente Barreira, Juan Antonio
A1 Korkian, Golnaz
A1 Rey, Solenne
A1 Cheymol, Benjamin
A1 Baylac, Maud
A1 Hubert, Guillaume
A1 Velazco, Raoul
AB A sensitivity characterization of a Xilinx Artix-7 FPGA against 14.2 MeV neutrons is presented. The content of the internal SRAMs and flip-flops were downloaded in a PC and compared with a golden version of it. Flipped cells were identified and classified as cells of the configuration RAM, BRAM, or flip-flops. SBUs and MCUs with multiplicities ranging from 2 to 8 were identified using a statistical method. Possible shapes of multiple events are also investigated, showing a trend to follow wordlines. Finally, MUSCA SEP3 was used to make assesment for actual environments and an improvement of SEU injection test is proposed.
PB IEEE-Inst Electrical Electronics Engineers Inc
SN 0018-9499
YR 2020
FD 2020
LK https://hdl.handle.net/20.500.14352/6088
UL https://hdl.handle.net/20.500.14352/6088
LA eng
NO Ministerio de Economía y Competitividad (MINECO)
NO IRT Nanoelec
DS Docta Complutense
RD 6 abr 2025