%0 Book Section
%T Work-in-progress: High-performance systolic hardware accelerator for RBLWE-based post-quantum cryptography
publisher Institute of Electrical and Electronics Engineers.
%D 2022
%U 978-1-6654-7294-4
%@ https://hdl.handle.net/20.500.14352/2512
%X Ring-Binary-Learning-with-Errors (RBLWE)-based post-quantum cryptography (PQC) is a promising scheme suitable for lightweight applications. This paper presents an efficient hardware systolic accelerator for RBLWE-based PQC, targeting highperformance applications. We have briefly given the algorithmic background for the proposed design. Then, we have transferred the proposed algorithmic operation into a new systolic accelerator. Lastly, field-programmable gate array (FPGA) implementation results have confirmed the efficiency of the proposed accelerator.
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