RT Book, Section
T1 A power-efficient and scalable load-store queue design
A1 Castro, F.
A1 Chaver Martínez, Daniel Ángel
A1 Piñuel Moreno, Luis
A1 Prieto Matías, Manuel
A1 Huang, M. C.
A1 Tirado Fernández, José Francisco
AB The load-store queue (LQ-SQ) of modem superscalar processors is responsible for keeping the order of memory operations. As the performance gap between processing speed and memory access becomes worse, the capacity requirements for the LQ-SQ increase, and its design becomes a challenge due to its CAM structure. In this paper we propose an efficient load-store queue state filtering mechanism that provides a significant energy reduction (on average 35% in the LSQ and 3.5% in the whole processor), and only incurs a negligible performance loss of less than 0.6%.
PB Springer-Verlag Berlin
SN 3-540-29013-3
YR 2005
FD 2005
LK https://hdl.handle.net/20.500.14352/53421
UL https://hdl.handle.net/20.500.14352/53421
LA eng
NO © Springer-Verlag Berlin Heidelberg 2005.We want to thank Simha Sethumadhavan for his helpful and thorough comments.International Workshop on Power and Timing Modeling, Optimization and Simulation (15th. sep 21-23, 2005.Lovaina, Belgica).
DS Docta Complutense
RD 7 abr 2025