TY  - CHAP
AU  - Castro, F.
AU  - Chaver Martínez, Daniel Ángel
AU  - Piñuel Moreno, Luis
AU  - Prieto Matías, Manuel
AU  - Huang, M. C.
AU  - Tirado Fernández, José Francisco
PY  - 2005
SN  - 3-540-29013-3
UR  - https://hdl.handle.net/20.500.14352/53421
AB  - The load-store queue (LQ-SQ) of modem superscalar processors is responsible for keeping the order of memory operations. As the performance gap between processing speed and memory access becomes worse, the capacity requirements for the LQ-SQ increase,...
LA  - eng
M2  - 1
PB  - Springer-Verlag Berlin
KW  - Computer science
KW  - hardware & architecture
KW  - theory & methods
KW  - Engineering
KW  - electrical & electronic
TI  - A power-efficient and scalable load-store queue design
TY  - book part
VL  - 3728
ER  -