RT Journal Article
T1 Low interface trap density in rapid thermally annealed Al/SiNx : H/InP metal-insulator-semiconductor devices
A1 Martil De La Plaza, Ignacio
A1 González Díaz, Germán
A1 Redondo, E.
A1 Blanco, N.
AB A minimum interface trap density of 10(12) eV(-1) cm(-2) was obtained on SiNx:H/InP metalinsulator-semiconductor structures without InP surface passivation. The SiNx:H gate insulator was obtained by the electron cyclotron resonance plasma method. This insulator was deposited in a single vacuum run and was composed of two layers with different nitrogen-to-silicon ratios. The first layer deposited onto the InP was grown with a nitrogen-to-silicon ratio of N/Si=1.55, whereas the second one was grown with a N/Si ratio of N/Si = 1.43. After the insulator deposition, rapid thermal annealing of the devices was performed at a constant annealing time of 30 s. The interface trap density minimum value was obtained at an optimum annealing temperature of 500 degrees C. Higher annealing temperatures promote thermal degradation of the interface and a sharp increase in the trap density.
PB Amer Inst Physics
SN 0003-6951
YR 1999
FD 1999-02-15
LK https://hdl.handle.net/20.500.14352/59284
UL https://hdl.handle.net/20.500.14352/59284
LA eng
NO © American Institute of Physics. The authors would like to thank C. A. I. de Implantación Iónica from the Universidad Complutense in Madrid for technical assistance with the ECR-CVD system.
DS Docta Complutense
RD 11 oct 2025