RT Journal Article
T1 Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration
A1 Imaña Pascual, José Luis
A1 Piñuel Moreno, Luis
A1 Yao-Ming Kuo, 
A1 Ruano Ramos, Óscar
A1 García Herrero, Francisco Miguel
AB Binary extension field arithmetic is widely used in several important applications such as error-correcting codes, cryptography and digital signal processing. Multiplication is usually considered the most important finite field arithmetic operation. Therefore efficient hardware architectures for multiplication are highly desired. In this brief, a new architecture for multiplication over finite fields generated by irreducible trinomials f(x)=xm+xt+1 is presented. The architecture here proposed is based on the use of a polynomial multiplier and a cyclic shift register that can perform the multiplication in t−1 clock cycles. The general architecture is applied to the trinomials recommended by NIST (National Institute of Standards and Technology). Furthermore, a RISC-V instruction set for the proposed multiplier is implemented and validated using VeeR-EL2 on a Nexys A7 FPGA. To the best knowledge of the authors, this is the first work that integrates the multiplication based on NIST trinomials into a RISC-V SoC. Results show an improvement of several orders of magnitude in terms of latency at a cost of less than 50% more of area.
PB Institute of Electrical and Electronics Engineers Inc.
YR 2024
FD 2024
LK https://hdl.handle.net/20.500.14352/110136
UL https://hdl.handle.net/20.500.14352/110136
LA eng
DS Docta Complutense
RD 18 dic 2025