RT Journal Article
T1 Simulating spin systems on IANUS, an FPGA-based computer
A1 Fernández Pérez, Luis Antonio
A1 Martín Mayor, Víctor
A1 Muñoz Sudupe, Antonio
A1 otros, ...
AB We describe the hardwired implementation of algorithms for Monte Carlo simulations of a large class of spin models. We have implemented these algorithms as VHDL codes and we have mapped them onto a dedicated processor based on a large FPGA device. The measured performance on one such processor is comparable to O(100) carefully programmed high-end PCs: it turns out to be even better for some selected spin models. We describe here codes that we are currently executing on the IANUS massively parallel FPGA-based system.
PB Elsevier Science Ltd
SN 0010-4655
YR 2008
FD 2008-02-01
LK https://hdl.handle.net/20.500.14352/51916
UL https://hdl.handle.net/20.500.14352/51916
LA eng
NO © 2007 Elsevier B.V. Artículo firmado por 18 autores. The help of G. Poli in the development of the IANUS Ethernet interface is warmly acknowledged.
DS Docta Complutense
RD 7 abr 2025