TY  - JOUR
AU  - Rodríguez Rodríguez, Roberto Alonso
AU  - Díaz, Javier
AU  - Castro Rodríguez, Fernando
AU  - Ibáñez, Pablo
AU  - Chaver Martínez, Daniel Ángel
AU  - Viñals, Víctor
AU  - Sáez Alcaide, Juan Carlos
AU  - Prieto Matías, Manuel
AU  - Piñuel Moreno, Luis
AU  - Monreal, Teresa
AU  - Llabería, José María
PY  - 2018
DO  - doi.org/10.1093/comjnl/bxx099
SN  - 0010-4620
UR  - https://hdl.handle.net/20.500.14352/94365
T2  - The Computer Journal
AB  - Various constraints of Static Random Access Memory (SRAM) are leading to consider new memory technologies as candidates for building on-chip shared last-level caches (SLLCs). Spin-Transfer Torque RAM (STT-RAM) is currently postulated as the prime...
LA  - eng
M2  - 856
PB  - Oxford University Press
KW  - STT-RAM
KW  - Reuse Detector
KW  - Reuse Locality
KW  - Write Filtering
KW  - Energy Savings
KW  - Performance
TI  - Reuse detector: improving the management of STT-RAM SLLCs
TY  - journal article
VL  - 61
ER  -