%0 Journal Article
%A Acciarito, Simone
%A Cardarilli, Gian Carlo
%A Cristini, Alessandro
%A Di Nunzio, Luca
%A Fazzolari, Rocco
%A Khanal, Gaurav Mani
%A Re, Marco
%A Susi, Gianluca
%T Hardware design of LIF with Latency neuron model with memristive STDP synapses
%D 2017
%@ 0720-5120
%U https://hdl.handle.net/20.500.14352/116839
%X In this paper, the hardware implementation of a neuromorphic system is presented. This system is composed of a Leaky Integrate-and-Fire with Latency (LIFL) neuron and a Spike-Timing Dependent Plasticity (STDP) synapse. LIFL neuron model allows to encode more information than the common Integrate-and-Fire models, typically considered for neuromorphic implementations. In our system LIFL neuron is implemented using CMOS circuits while memristor is used for the implementation of the STDP synapse. A description of the entire circuit is provided. Finally, the capabilities of the proposed architecture have been evaluated by simulating a motif composed of three neurons and two synapses. The simulation results confirm the validity of the proposed system and its suitability for the design of more complex spiking neural networks.
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