RT Journal Article
T1 Hardware design of LIF with Latency neuron model with memristive STDP synapses
A1 Acciarito, Simone
A1 Cardarilli, Gian Carlo
A1 Cristini, Alessandro
A1 Di Nunzio, Luca
A1 Fazzolari, Rocco
A1 Khanal, Gaurav Mani
A1 Re, Marco
A1 Susi, Gianluca
AB In this paper, the hardware implementation of a neuromorphic system is presented. This system is composed of a Leaky Integrate-and-Fire with Latency (LIFL) neuron and a Spike-Timing Dependent Plasticity (STDP) synapse. LIFL neuron model allows to encode more information than the common Integrate-and-Fire models, typically considered for neuromorphic implementations. In our system LIFL neuron is implemented using CMOS circuits while memristor is used for the implementation of the STDP synapse. A description of the entire circuit is provided. Finally, the capabilities of the proposed architecture have been evaluated by simulating a motif composed of three neurons and two synapses. The simulation results confirm the validity of the proposed system and its suitability for the design of more complex spiking neural networks.
PB Elsevier
SN 0720-5120
YR 2017
FD 2017-09
LK https://hdl.handle.net/20.500.14352/116839
UL https://hdl.handle.net/20.500.14352/116839
LA eng
NO Acciarito, S., Cardarilli, G.C., Cristini, A., Nunzio, L.D., Fazzolari, R., Khanal, G.M., Re, M., Susi, G., 2017. Hardware design of LIF with Latency neuron model with memristive STDP synapses. Integration 59, 81–89. https://doi.org/10.1016/j.vlsi.2017.05.006
NO Se deposita la versión aceptada (postprint) del artículo
DS Docta Complutense
RD 4 may 2025