RT Journal Article
T1 Single Events in a COTS Soft-Error Free SRAM at Low Bias Voltage Induced by 15-MeV Neutrons
A1 Clemente Barreira, Juan Antonio
A1 Franco Peláez, Francisco Javier
A1 Villa, Francesca
A1 Baylac, Maud
A1 Ramos Vargas, Pablo Francisco
A1 Vargas Vallejo, Vanessa Carolina
A1 Mecha López, Hortensia
A1 Agapito Serrano, Juan Andrés
A1 Velazco, Raoul
AB This paper presents an experimental study of the sensitivity to 15-MeV neutrons of Advanced Low Power SRAMs (A-LPSRAM) at low bias voltage little above the threshold value that allows the retention of data.  This family of memories is characterized by a 3D structure to minimize the area penalty and to cope with latchups, as well as by the presence of integrated capacitors to hinder the occurrence of single event upsets. In low voltage static tests, classical single event upsets were a minor source of errors, but other unexpected phenomena such as clusters of bitflips and hard errors turned out to be the origin of hundreds of bitflips. Besides, errors were not observed in dynamic tests at nominal voltage. This behavior is clearly different than that of standard bulk CMOS SRAMs, where thousands of errors have been reported.
PB IEEE-Inst Electrical Electronics Engineers Inc
SN 0018-9499
YR 2016
FD 2016-08-16
LK https://hdl.handle.net/20.500.14352/18945
UL https://hdl.handle.net/20.500.14352/18945
LA eng
NO © IEEE-Inst Electrical Electronics Engineers.This work was supported in part by the Spanish MCINN project TIN2013-40968-P, by the Secretaría de Educación Superior Ciencia Tecnología e Innovación del Ecuador (SENESCYT), and by the “José Castillejo” mobility grant for professors and researchers.
NO Ministerio de Economía y Competitividad (MINECO)
NO Secretaría de Educación Superior Ciencia Tecnología e Innovación del Ecuador (SENESCYT)
NO Programa "José Castillejo" para movilidad de profesores
NO Ministerio de Educación, Cultura y Deporte (MECD), España
DS Docta Complutense
RD 9 abr 2025