%0 Conference Paper
%A Igual, Francisco D.
%A Costero Valero, Luis María
%A Igual Peña, Francisco Daniel
%A Olcoz Herrero, Katzalin
%A Tirado Fernández, José Francisco
%T Energy efficiency optimization of task-parallel codes on asymmetric architectures
%D 2017
%U https://hdl.handle.net/20.500.14352/101021
%X We present a family of policies that, integrated within a runtime task scheduler (Nanox), pursue the goal of improving the energy efficiency of task-parallel executions with no intervention from the programmer. The proposed policies tackle the problem by modifying the core operating frequency via DVFS mechanisms, or by enabling/disabling the mapping of tasks to specific cores at selected execution points, depending on the internal status of the scheduler. Experimental results on an asymmetric SoC (Exynos 5422) and for a specific operation (Cholesky factorization) reveal gains up to 29% in terms of energy efficiency and considerable reductions in average power
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