RT Conference Proceedings
T1 Energy efficiency optimization of task-parallel codes on asymmetric architectures
A1 Igual, Francisco D.
A1 Costero Valero, Luis María
A1 Igual Peña, Francisco Daniel
A1 Olcoz Herrero, Katzalin
A1 Tirado Fernández, José Francisco
AB We present a family of policies that, integrated within a runtime task scheduler (Nanox), pursue the goal of improving the energy efficiency of task-parallel executions with no intervention from the programmer. The proposed policies tackle the problem by modifying the core operating frequency via DVFS mechanisms, or by enabling/disabling the mapping of tasks to specific cores at selected execution points, depending on the internal status of the scheduler. Experimental results on an asymmetric SoC (Exynos 5422) and for a specific operation (Cholesky factorization) reveal gains up to 29% in terms of energy efficiency and considerable reductions in average power
SN 978-1-5386-3250-5
YR 2017
FD 2017
LK https://hdl.handle.net/20.500.14352/101021
UL https://hdl.handle.net/20.500.14352/101021
LA eng
DS Docta Complutense
RD 5 abr 2025