RT Journal Article
T1 LFSR-based bit-serial GF(^2m) multipliers using irreducible trinomials
A1 Imaña Pascual, José Luis
AB In this article, a new architecture of bit-serial polynomial basis (PB) multipliers over the binary extension field GF(^2m) generated by irreducible trinomials is presented. Bit-serial GF(^2m) PB multiplication offers a performance/area trade-off that is very useful in resource constrained applications. The architecture here proposed is based on LFSR (Linear-Feedback Shift Register) and can perform a multiplication in m clock cycles with a constant propagation delay of T_A + T_X. These values match the best time results found in the literature for bit-serial PB multipliers with a slight reduction of the space complexity. Furthermore, the proposed architecture can perform the multiplication of two operands for t different finite fields GF(^2m) generated by t irreducible trinomials simultaneously in m clock cycles with the inclusion of t(m - 1) flipflops and tm XOR gates.
PB Institute of Electrical and Electronics Engineers (IEEE)
SN 0018-9340
YR 2021
FD 2021-01-01
LK https://hdl.handle.net/20.500.14352/7669
UL https://hdl.handle.net/20.500.14352/7669
LA eng
NO © 2021 Institute of Electrical and ElectronicsThis work was supported in part by the Spanish MINECO and CM under Grant S2018/TCS-4423, Grant TIN 2015-65277-R, and Grant RTI2018-093684-B-I00.
NO Ministerio de Economía y Competitividad (MINECO)
NO Comunidad de Madrid
DS Docta Complutense
RD 8 may 2024