RT Journal Article
T1 Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems
A1 Clemente Barreira, Juan Antonio
A1 Gran, Rubén
A1 Chocano Gómez, Abel
A1 Prado, Carlos del
A1 Resano, Javier
AB The efficiency of the reconfiguration process in modern FPGAs can improve drastically if an on-chip configuration memory is included in the system because it can reduce both the reconfiguration latency and its energy consumption. However, FPGA on-chip memory resources are very limited. Thus, it is very important to manage them effectively in order to improve the reconfiguration process as much as possible even when the size of the on-chip configuration memory is small. This paper presents a hardware implementation of an on-chip configuration memory controller that efficiently manages run-time reconfigurations. In order to optimize the use of the on-chip memory, this controller includes support to deal with configurations that have been divided into blocks of customizable size. When a reconfiguration must be carried out, our controller provides the blocks stored on-chip and looks for the remaining blocks by accessing to the off-chip configuration memory. Moreover, it dynamically decides which blocks must be stored on-chip. To this end, the designed controller implements a simple but efficient technique that allows maximizing the benefits of the on-chip memories. Experimental results will demonstrate that its implementation cost is very affordable and that it introduces negligible run-time management overheads.
PB IEEE
SN 1063-8210
YR 2015
FD 2015-04-16
LK https://hdl.handle.net/20.500.14352/24086
UL https://hdl.handle.net/20.500.14352/24086
LA spa
NO “© © 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.”
NO Unión Europea. FP7
NO Ministerio de Economía y Competitividad (MINECO)
NO Gobierno de Aragón
DS Docta Complutense
RD 27 abr 2025