%0 Journal Article
%A Clemente Barreira, Juan Antonio
%A Mansour, Wassim
%A Ayoubi, Rafic
%A Serrano, Felipe
%A Mecha López, Hortensia
%A Ziade, Haissam
%A El Falou, Wassim
%A Velazco, Raoul
%T Hardware Implementation of a Fault-Tolerant Hopfield Neural Network on FPGAs
%D 2016
%@ 0925-2312
%U https://hdl.handle.net/20.500.14352/24602
%X This letter presents an FPGA implementation of a fault-tolerant Hopfield NeuralNetwork (HNN). The robustness of this circuit against Single Event Upsets (SEUs) and Single Event Transients (SETs) has been evaluated. Results show the fault tolerance of the proposed design, compared to a previous non fault- tolerant implementation and a solution based on triple modular redundancy (TMR) of a standard HNN design.
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