RT Journal Article
T1 Hardware Implementation of a Fault-Tolerant Hopfield Neural Network on FPGAs
A1 Clemente Barreira, Juan Antonio
A1 Mansour, Wassim
A1 Ayoubi, Rafic
A1 Serrano, Felipe
A1 Mecha López, Hortensia
A1 Ziade, Haissam
A1 El Falou, Wassim
A1 Velazco, Raoul
AB This letter presents an FPGA implementation of a fault-tolerant Hopfield NeuralNetwork (HNN). The robustness of this circuit against Single Event Upsets (SEUs) and Single Event Transients (SETs) has been evaluated. Results show the fault tolerance of the proposed design, compared to a previous non fault- tolerant implementation and a solution based on triple modular redundancy (TMR) of a standard HNN design.
PB Elsevier
SN 0925-2312
YR 2016
FD 2016-01-01
LK https://hdl.handle.net/20.500.14352/24602
UL https://hdl.handle.net/20.500.14352/24602
LA eng
NO Ministerio de Educación, Cultura y Deportes
NO Mobility grant for professors and researchers "José Castillejo"
DS Docta Complutense
RD 9 abr 2025