RT Journal Article
T1 Reliability of Error Correction Codes Against Multiple Events by Accumulation
A1 Clemente Barreira, Juan Antonio
A1 Rezaei, Mohammadreza
A1 Franco Peláez, Francisco Javier
AB Modern nanoscale devices with storage capacity typically implement error correction codes (ECCs) in order to cope with the effects of natural radiation. Thus, different state-of-the-art ECC techniques aim at preventing data corruption when different numbers of errors (or bitflips) occur in the same logical memory word. However, even though bit interleaving prevents a single particle (such as a proton or a neutron) from flipping several cells in the same word, it cannot be discarded that two independent events may affect nearby cells in the same word and, therefore, would provoke a multiple bit upset (MBU) or equivalent. This article studies the reliability of various state-of-the-art ECC techniques designed for memories to maintain their data integrity under radiation or any other hazardous conditions, where said event accumulation is likely to occur. For this purpose, a set of easy-to-use equations will be provided to estimate the probability of error occurrence in a memory that implements different ECCs, as a function of the number of accumulated bitflips, size of the memory, and word size.
PB IEEE-Inst Electrical Electronics Engineers Inc
SN 0018-9499
LK https://hdl.handle.net/20.500.14352/65264
UL https://hdl.handle.net/20.500.14352/65264
LA eng
NO Ministerio de Economía y Competitividad (MINECO)
DS Docta Complutense
RD 30 abr 2024