RT Journal Article
T1 High-speed polynomial basis multipliers over GF(2^m) for special pentanomials
A1 Imaña Pascual, José Luis
AB Efficient hardware implementations of arithmetic operations in the Galois field GF(2^m) are highly desirable for several applications, such as coding theory, computer algebra and cryptography. Among these operations, multiplication is of special interest because it is considered the most important building block. Therefore, high-speed algorithms and hardware architectures for computing multiplication are highly required. In this paper, bit-parallel polynomial basis multipliers over the binary field GF(2^m) generated using type II irreducible pentanomials are considered. The multiplier here presented has the lowest time complexity known to date for similar multipliers based on this type of irreducible pentanomials.
PB IEEE-Inst Electrical Electronics Engineers Inc.
SN 1549-8328
YR 2016
FD 2016-01
LK https://hdl.handle.net/20.500.14352/24434
UL https://hdl.handle.net/20.500.14352/24434
LA eng
NO 1.	H. A. Curtis, A New Approach to the Design of Switching Circuits, 1962, Van Nostrand2.	J. Lin, J. Sha, Z. Wang and L. Li, "Efficient decoder design for nonbinary quasicyclic LDPC codes", IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 5, pp. 1071-1082, 2010.3.	T.-C. Chen, S.-W. Wei and H.-J. Tsai, "Arithmetic unit for finite field GF(2^m)", IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 3, pp. 828-837, 2008.4.	J. L. Imaña, "Low latency GF(2^m) polynomial basis multiplier", IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 5, pp. 935-946, 2011.5.	M. A. Hasan and M. Ebtedaei, "Efficient architectures for computations over variable dimensional galois fields", IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 45, no. 11, pp. 1205-1211, 1998.6.	J. L. Imaña, R. Hermida and F. Tirado, "Low complexity bit-parallel polynomial basis multipliers over binary fields for special irreducible pentanomials", Integration, vol. 46, pp. 197-210, 2013.7.	P. K. Meher, "Systolic and super-systolic multipliers for finite field GF(2^m) based on irreducible trinomials", IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 4, pp. 1031-1040, 2008.8.	C. L. Wang and J. L. Lin, "Systolic array implementation of multipliers for finite fields GF(2^m)", IEEE Trans. Circuits Syst., vol. 38, no. 7, pp. 796-800, 1991.9.	J. L. Imaña, "Efficient polynomial basis multipliers for Type II irreducible pentanomials", IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 59, no. 11, pp. 795-799, 2012.10.	R. Azarderakhsh, D. Jao and H. Lee, "Common subexpression algorithms for space-complexity reduction of gaussian normal basis multiplication", IEEE Trans. Inf. Theory, vol. 61, no. 5, pp. 2357-2369, 2015.11.	S. T. J. Fenn, M. Benaissa and D. Taylor, " GF(2^m) multiplication and division over the dual basis", IEEE Trans. Comput., vol. 45, no. 3, pp. 319-327, 1996.12.	A. Reyhani-Masoleh and M. A. Hasan, "Low complexity bit parallel architectures for polynomial basis multiplication over GF(2^m)", IEEE Trans. Comput., vol. 53, no. 8, pp. 945-959, 2004.13.	T. Zhang and K. K. Parhi, "Systematic design of original and modified mastrovito multipliers for general irreducible polynomials", IEEE Trans. Comput., vol. 50, no. 7, pp. 734-749, 2001.14.	H. Fan and Y. Dai, "Fast bit parallel GF(2^m) multiplier for all trinomials", IEEE Trans. Comput., vol. 54, no. 4, pp. 485-490, 2005.15.	E. D. Mastrovito, "VLSI architectures for multiplication over finite fields GF(2^m)", Proc. 6th Int'l Conf. Appl. Algebra, Algebraic Algorithms, Error-Correcting Codes (AAECC-6), pp. 297-309.16.	K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation, 1999, Wiley.17.	A. Halbutogullari and Ç. K. Koç, "Mastrovito multiplier for general irreducible polynomials", IEEE Trans. Comput., vol. 49, no. 5, pp. 503-518, 2000.18.	F. Rodríguez-Henríquez and Ç. K. Koç, "Parallel multipliers based on special irreducible pentanomials", IEEE Trans. Comput., vol. 52, no. 12, pp. 1535-1542, 2003.19.	V. B. Afanasyev, "Complexity of VLSI implementation of finite field arithmetic", Proc. II Int. Workshop Algebraic Combinatorial Coding Theory, pp. 6-7.20.	J. L. Imaña, R. Hermida and F. Tirado, "Low complexity bit-parallel multipliers based on a class of irreducible pentanomials", IEEE Trans. Very Large Scale Integr. (VLSI) Systems, vol. 14, no. 12, pp. 1388-1393, 2006.21.	S.-M. Park, K.-Y. Chang, D. Hong and C. Seo, "New efficient bit-parallel polynomial basis multiplier for special pentanomials", Integration, vol. 47, pp. 130-139, 2014.
NO © 2015 IEEE.This work was supported by the Spanish Government under Research Grants CICYT TIN2008-00508 and TIN2012-32180. This paper was recommended by Associate Editor S. Ghosh.
NO Comisión Interministerial de Ciencia y Tecnología (CICYT), España
DS Docta Complutense
RD 30 abr 2024