RT Journal Article
T1 The RISC-V FPGA (RVfpga) teaching package
A1 Chaver Martínez, Daniel Ángel
A1 Harris, Sarah
A1 Piñuel Moreno, Luis
A1 Kindgren, Olof
A1 Kakakhel, Zubair
A1 Owen, Chris
A1 Kravitz, Roy
A1 Gómez Pérez, José Ignacio
A1 Castro Rodríguez, Fernando
A1 Olcoz Herrero, Katzalin
A1 Villalba Moreno, Julio
A1 Grinshpun, Alexander
A1 Gabbay, Freddu
A1 Seed, Luke
A1 Duarte, Rui
A1 López, Manuel
A1 Alonso, Óscar
A1 Owen, Robert
AB RISC-V is a free and open-standard ISA based on RISC principles, allowing anyone to design, manufacture, and sell RISC-V chips and software. Its flexibility and growing ecosystem have made it popular in research, education, and industry, increasing the need for educational materials. This paper provides an in-depth description of the RVfpga course, which offers a solid introduction to computer architecture using the RISC-V instruction set and FPGA technology. It focuses on providing hands-on experience with real-world RISC-V cores, the VeeR EH1 and EL2 cores, developed by Western Digital and hosted by ChipsAlliance. The course targets students and educators in computing-related fields, enabling them to integrate practical RISC-V knowledge into their curricula. The course materials, which include detailed labs, setup guides, and the full SoC source code in System Verilog, are available for free. Students learn to compile, debug, and run C and assembly programs, to interact with built-in peripherals, to extend the SoC, and to explore microarchitectural features.
PB Institute of Electrical and Electronics Engineers
YR 2026
FD 2026-02-06
LK https://hdl.handle.net/20.500.14352/132377
UL https://hdl.handle.net/20.500.14352/132377
LA eng
NO D. Chaver et al., "The RISC-V FPGA (RVfpga) Teaching Package," in IEEE Access, vol. 14, pp. 18455-18475, 2026, doi: 10.1109/ACCESS.2026.3658743.
NO © 2026 The Authors.
NO Ministerio de Ciencia, Innovación y Universidades (España)
NO Agencia Estatal de Investigación
NO European Commission
NO Imagination Technologies
NO University of Nevada, Las Vegas
NO Interuniversity Microelectronics Centre (Belgium)
DS Docta Complutense
RD 29 mar 2026