RT Journal Article
T1 Power profiling-guided floorplanner for 3D multi-processor systems-on-chip
A1 Arnaldo, Ignacio
A1 Higalgo, J. Ignacio
A1 Risco Martín, José Luis
A1 Ayala Rodrigo, José Luis
AB Three-dimensional (3D) integration has become one of the most promising techniques for the development of future multi-core processors, since it improves performance and reduces power consumption by decreasing global wire length. However, 3D integration causes serious thermal problems because the closer proximity of heat generating dies makes existing thermal hotspots more severe. Thermal-aware floorplanners can play an important role to improve the thermal profile, but they have failed in considering the dynamic power profiles of the applications. This study proposes a novel thermal-aware floorplanner guided by the power profiling of a set of benchmarks that are representative of the application scope. The results show how our approach outperforms the thermal metrics as compared with the worst-case scenario usually considered in ‘traditional’ thermal-aware floorplanners.
PB The Institution of Engineering and Technology
YR 2012
FD 2012
LK https://hdl.handle.net/20.500.14352/119961
UL https://hdl.handle.net/20.500.14352/119961
LA eng
DS Docta Complutense
RD 22 ene 2026