%0 Journal Article
%A Yao-Ming Kuo
%A García Herrero, Francisco Miguel
%A Ruano Ramos, Óscar
%A Maestro De La Cuerda, Juan Antonio
%A Flanagan, Mark
%T Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension
%D 2023
%U https://hdl.handle.net/20.500.14352/110137
%X The Consultative Committee for Space Data Systems (CCSDS) recommends the use of short-block length Bose-Chaudhuri-Hocquenghem and binary low-density parity-check codes. Despite the high error-correction capacity of nonbinary low-density parity-check (NB-LDPC) codes, they have not yet been considered due to their high decoding complexity. In this article, the feasibility of NB-LDPC coding for space telecommand link applications using an RISC-V soft-core processor plus a vector coprocessor is demonstrated. The purpose of this article is to avoid the need for a dedicated decoder hardware, and thus, the customized general-purpose processor that performs decoding can be reconfigured to perform other important onboard tasks. In this way, the logic utilization and power consumption can be reduced since more functionalities can be assumed by the onboard processor. The method of acceleration of an NB-LDPC decoder over GF(16) using the RISC-V vector extension is demonstrated, and a throughput of 8.48 kb/s is achieved for the forward-backward implementation of the min-max decoding algorithm, which is compatible with the low-rate and mid-rate telecommand systems recommended by the CCSDS.
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