RT Journal Article
T1 Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension
A1 Yao-Ming Kuo, 
A1 García Herrero, Francisco Miguel
A1 Ruano Ramos, Óscar
A1 Maestro De La Cuerda, Juan Antonio
A1 Flanagan, Mark
AB The Consultative Committee for Space Data Systems (CCSDS) recommends the use of short-block length Bose-Chaudhuri-Hocquenghem and binary low-density parity-check codes. Despite the high error-correction capacity of nonbinary low-density parity-check (NB-LDPC) codes, they have not yet been considered due to their high decoding complexity. In this article, the feasibility of NB-LDPC coding for space telecommand link applications using an RISC-V soft-core processor plus a vector coprocessor is demonstrated. The purpose of this article is to avoid the need for a dedicated decoder hardware, and thus, the customized general-purpose processor that performs decoding can be reconfigured to perform other important onboard tasks. In this way, the logic utilization and power consumption can be reduced since more functionalities can be assumed by the onboard processor. The method of acceleration of an NB-LDPC decoder over GF(16) using the RISC-V vector extension is demonstrated, and a throughput of 8.48 kb/s is achieved for the forward-backward implementation of the min-max decoding algorithm, which is compatible with the low-rate and mid-rate telecommand systems recommended by the CCSDS.
PB Institute of Electrical and Electronics Engineers Inc.
YR 2023
FD 2023
LK https://hdl.handle.net/20.500.14352/110137
UL https://hdl.handle.net/20.500.14352/110137
LA eng
DS Docta Complutense
RD 8 abr 2025