2026-06-29T08:16:48Zhttps://docta.ucm.es/rest/oai/request

oai:docta.ucm.es:20.500.14352/1010212025-07-15T15:06:40Zcom_20.500.14352_14col_20.500.14352_15

Energy efficiency optimization of task-parallel codes on asymmetric architectures Costero Valero, Luis María Igual, Francisco D. Igual Peña, Francisco Daniel Olcoz Herrero, Katzalin Tirado Fernández, José Francisco Hardware Programación de ordenadores (Informática) 3304.06 Arquitectura de Ordenadores We present a family of policies that, integrated within a runtime task scheduler (Nanox), pursue the goal of improving the energy efficiency of task-parallel executions with no intervention from the programmer. The proposed policies tackle the problem by modifying the core operating frequency via DVFS mechanisms, or by enabling/disabling the mapping of tasks to specific cores at selected execution points, depending on the internal status of the scheduler. Experimental results on an asymmetric SoC (Exynos 5422) and for a specific operation (Cholesky factorization) reveal gains up to 29% in terms of energy efficiency and considerable reductions in average power Depto. de Arquitectura de Computadores y Automática Fac. de Informática TRUE pub 2024-02-09T16:42:23Z 2024-02-09T16:42:23Z 2017 conference paper VoR https://hdl.handle.net/20.500.14352/101021 XXXX-XXXX eng L. Costero, F. D. Igual, K. Olcoz and F. Tirado, "Energy Efficiency Optimization of Task-Parallel Codes on Asymmetric Architectures," 2017 International Conference on High Performance Computing & Simulation (HPCS), Genoa, Italy, 2017, pp. 402-409, doi: 10.1109/HPCS.2017.67 restricted access application/pdf