2026-06-29T07:24:44Zhttps://docta.ucm.es/rest/oai/request

oai:docta.ucm.es:20.500.14352/1101362024-11-07T00:58:09Zcom_20.500.14352_14col_20.500.14352_15

Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration Imaña Pascual, José Luis Piñuel Moreno, Luis Yao-Ming Kuo Ruano Ramos, Óscar García Herrero, Francisco Miguel Hardware 33 Ciencias Tecnológicas Binary extension field arithmetic is widely used in several important applications such as error-correcting codes, cryptography and digital signal processing. Multiplication is usually considered the most important finite field arithmetic operation. Therefore efficient hardware architectures for multiplication are highly desired. In this brief, a new architecture for multiplication over finite fields generated by irreducible trinomials f(x)=xm+xt+1 is presented. The architecture here proposed is based on the use of a polynomial multiplier and a cyclic shift register that can perform the multiplication in t−1 clock cycles. The general architecture is applied to the trinomials recommended by NIST (National Institute of Standards and Technology). Furthermore, a RISC-V instruction set for the proposed multiplier is implemented and validated using VeeR-EL2 on a Nexys A7 FPGA. To the best knowledge of the authors, this is the first work that integrates the multiplication based on NIST trinomials into a RISC-V SoC. Results show an improvement of several orders of magnitude in terms of latency at a cost of less than 50% more of area. Depto. de Arquitectura de Computadores y Automática Fac. de Informática TRUE pub 2024-11-06T16:27:06Z 2024-11-06T16:27:06Z 2024 journal article VoR https://hdl.handle.net/20.500.14352/110136 XXXX-XXXX 10.1109/TCSII.2024.3369103 eng PID2021-123041OB-I00 MCIN/AEI/10.13039/501100011033 Attribution-NonCommercial-NoDerivatives 4.0 International http://creativecommons.org/licenses/by-nc-nd/4.0/ open access application/pdf Institute of Electrical and Electronics Engineers Inc.