2026-06-29T01:18:30Zhttps://docta.ucm.es/rest/oai/request

oai:docta.ucm.es:20.500.14352/1132892025-03-18T12:25:39Zcom_20.500.14352_14col_20.500.14352_15

00925njm 22002777a 4500 dc Cuesta-Infante, Alfredo author Colmenar, J. Manuel author Bankovic, Zorana author Zapater, Marina author Hidalgo, J. Ignacio author Moya, José M. author Risco Martín, José Luis author Ayala Rodrigo, José Luis author 2015 Constant necessity of improving performance has brought the invention of 3D chips. The improvement is achieved due to the reduction of wire length, which results in decreased nterconnection delay. However, 3D stacks have less heat dissipation due to the inner layers, which leads to increased temperature and the appearance of hot spots. This problem can be mitigated through appropriate floorplanning. For this reason, in this work we present and compare five different solutions for floorplanning of 3D chips. Each solution uses a different representation, and all are based on meta-heuristic algorithms, namely three of them are based on simulated annealing, while two other are based on evolutionary algorithms. The results show great capability of all the solutions in optimizing temperature and wire length, as they all exhibit significant improvements comparing to the benchmark floorplans. 10.1016/j.neucom.2014.06.078 https://hdl.handle.net/20.500.14352/113289 https://doi.org/10.1016/j.neucom.2014.06.078 Comparative study of meta-heuristic 3D floorplanning algorithms