2026-06-26T20:32:06Zhttps://docta.ucm.es/rest/oai/request

oai:docta.ucm.es:20.500.14352/139942023-09-07T16:20:09Zcom_20.500.14352_14col_20.500.14352_21

Reconfigurable implementation of GF(2^m) bit-parallel multipliers Imaña Pascual, José Luis Hardware implementations of arithmetic operations over binary finite fields GF(2^m) are widely used in several important applications, such as cryptography, digital signal processing and error-control codes. In this paper, efficient. reconfigurable implementations of bit-parallel canonical basis multipliers over binary fields generated by type II irreducible pentanomials f_(y) = y^m + y^(n+2) + y^(n+1) + y^n + 1 are presented. These pentanomials are important because all five binary fields recommended by NIST for ECDSA can be constructed using such polynomials. In this work, a new approach for CF(2^m) multiplication based on type II pentanomials is given and several post-place and route implementation results in Xilinx Artix-7 FPGA are reported. Experimental results show that the proposed multiplier implementations improve the area x time parameter when compared with similar multipliers found in the literature. 2023-06-17T14:17:31Z 2023-06-17T14:17:31Z 2023-06-17T14:17:31Z 2018-04-23 book part https://hdl.handle.net/20.500.14352/13994 XXXX-XXXX 10.23919/DATE.2018.8342134 eng Design Automation and Test in Europe Conference and Exhibition (TIN 2015-65277-R; TIN2012-32180) open access IEEE