2026-07-30T02:45:50Zhttps://docta.ucm.es/rest/oai/request
oai:docta.ucm.es:20.500.14352/352602023-08-28T15:09:31Zcom_20.500.14352_14col_20.500.14352_15
Docta Complutense author Clemente Barreira, Juan Antonio author Beretta, Ivan author Rana, Vincenzo author Atienza, David author Sciuto, Donatella 2023-06-19T15:04:10Z 2023-06-19T15:04:10Z 2014-06-01 1936-7406 10.1145/2611562 https://hdl.handle.net/20.500.14352/35260 http://dx.doi.org/10.1145/2611562 Reconfigurable platforms are a promising technology that offers an interesting trade-off between flexibility and performance, which many recent embedded system applications demand, especially in fields such as multimedia processing. These applications typically involve multiple ad-hoc tasks for hardware acceleration, which are usually represented using formalisms such as Data Flow Diagrams (DFDs), Data Flow Graphs (DFGs), Control and Data Flow Graphs (CDFGs) or Petri Nets. However, none of these models is able to capture at the same time the pipeline behavior between tasks (that therefore can coexist in order to minimize the application execution time), their communication patterns, and their data dependencies. This paper proves that the knowledge of all this information can be effectively exploited to reduce the resource requirements and the timing performance of modern reconfigurable systems, where a set of hardware accelerators is used to support the computation. For this purpose, this paper proposes a novel task representation model, named Temporal Constrained Data Flow Diagram (TCDFD), which includes all this information. This paper also presents a mapping-scheduling algorithm that is able to take advantage of the new TCDFD model. It aims at minimizing the dynamic reconfiguration overhead while meeting the communication requirements among the tasks. Experimental results show that the presented approach achieves up to 75% of resources saving and up to 89% of reconfiguration overhead reduction with respect to other state-of-the-art techniques for reconfigurable platforms. spa A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable Platforms journal article URL https://docta.ucm.es/bitstreams/7a167513-58bf-49c1-9d77-d3e2e7a4cbd6/download File MD5 7fc59c8bda21a0ad4e14f00ba724e10b 1337805 application/pdf A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable Platforms.pdf URL https://docta.ucm.es/bitstreams/b04080f2-327d-4f68-9ab7-cfabb35c96f4/download File MD5 920e5a127779c43c7ac7c8b4fa65bb7d 101101 text/plain A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable Platforms.pdf.txt