2026-07-20T01:04:38Zhttps://docta.ucm.es/rest/oai/requestoai:docta.ucm.es:20.500.14352/44182023-08-28T13:14:40Zcom_20.500.14352_14col_20.500.14352_15
Docta Complutense
author
Clemente Barreira, Juan Antonio
author
Hubert, Guillaume
author
Rezaei, Mohammadreza
author
Franco Peláez, Francisco Javier
author
Mecha López, Hortensia
2023-06-16T14:15:51Z
2023-06-16T14:15:51Z
2021-07-26
0018-9499
10.1109/TNS.2021.3099202
https://hdl.handle.net/20.500.14352/4418
https://ieeexplore.ieee.org/document/9493198
This paper presents an analysis of the multiple events (and more specifically, Multiple Cell Upsets or MCUs) that may occur at successive generations of bulk CMOS SRAMs operating under harsh conditions, such as in avionics or space. Such MCU distribution is greatly impacted by the bitcell topology, which, in the International Technology Roadmap for Semiconductors (ITRS) / International Roadmap for Devices and Systems (IRDS) history, experienced a drastic change in the transition between the 90-nm and the 65-nm nodes. Experimental results obtained from proton and neutron accelerators, along with predictions issued from the MUSCA-SEP3 modeling tool, are provided. Various COTS Static Random Access Memories (SRAMs) manufactured by Infineon in bulk CMOS 130-nm nodes down to the 65-nm one were used as targets for the experimental results. Finally, MUSCA-SEP3 was also used to analyze and discuss scaling trends on more modern nodes (45-nm down to 14-nm).
eng
Impact of the Bitcell Topology on the Multiple Cell Upsets Observed in VLSI Nanoscale SRAMs
journal article
URL
https://docta.ucm.es/bitstreams/8b893cd9-aa4c-4f1e-8e8c-47a470210858/download
File
MD5
e74d41e49d81ef17570a8d17f29002f2
774115
application/pdf
_TNS2020__Impact_of_the_Bitcell_Topology_on_the_Multiple_Cell_Upsets_Observed_in_VLSI_nanoscale_SRAMs.pdf