Imaña Pascual, José Luis2023-06-172023-06-172018-060018-934010.1109/TC.2017.2778730https://hdl.handle.net/20.500.14352/13330©2018 IEEE Computer Society This work has been supported by the EU (FEDER) and the Spanish MINECO, under grants TIN 2015-65277-R and TIN2012-32180.In this paper, a fast implementation of bit-parallel polynomial basis (PB) multipliers over the binary extension field GF(2^m) generated by type-I irreducible pentanomials is presented. Explicit expressions for the coordinates of the multipliers and a detailed example are given. Complexity analysis shows that the multipliers here presented have the lowest delay in comparison to similar bit-parallel PB multipliers found in the literature based on this class of irreducible pentanomials. In order to prove the theoretical complexities, hardware implementations over Xilinx FPGAs have also been performed. Experimental results show that the approach here presented exhibits the lowest delay with a balanced Area x Time complexity when it is compared with similar multipliers.engjournal articlehttp://dx.doi.org/10.1109/TC.2017.2778730https://ieeexplore.ieee.orgopen access004.8General irreducible polynomialsMastrovito multiplierGf(2^m)TrinomialsDesignFieldsMultipliersBit-parallelPolynomial basisPentanomialsInteligencia artificial (Informática)1203.04 Inteligencia Artificial