Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 FPGA

Olivito, JavierSerrano, FelipeClemente Barreira, Juan AntonioMecha, HortensiaResano, Javier2023-06-172023-06-172018-01-161751-860110.1049/iet-cdt.2016.0095https://hdl.handle.net/20.500.14352/11976In this paper we have evaluated the overhead and the tradeoffs of a set of components usually included in a system with run-time partial reconfiguration implemented on a Xilinx Virtex-5. Our analysis shows the benefits of including a scratchpad memory inside the reconfiguration controller in order to improve the efficiency of the reconfiguration process. We have designed a simple controller for this scratchpad that includes support for prefetching and caching in order to further reduce both the energy and latency overhead.engAnalysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 FPGAjournal articlehttp://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2016.0095open accessCircuitos integradosHardwareElectrónica (Informática)2203.07 Circuitos Integrados2203 Electrónica