Bao, TianyouImaña Pascual, José LuisHe, PengzhouXie, Jiafeng2023-06-162023-06-162022-11-14978-1-6654-7294-410.1109/CODES-ISSS55005.2022.00009https://hdl.handle.net/20.500.14352/2512©2022. International Conference On Hardware/Software Codesign And System Synthesis (CODES+ISSS) (2022. Shanghay) ISSN: 2832-6466; ISSN e-:2832-6474 J. Xie was supported by NSF SaTC-2020625 and in part by NIST-60NANB20D203. J.L. Imaña was supported by PID2021-123041OB-I00 funded by MCIN/AEI/10.13039/501100011033 and by “ERDF A way of making Europe”, and by the CM under grant S2018/TCS-4423.Ring-Binary-Learning-with-Errors (RBLWE)-based post-quantum cryptography (PQC) is a promising scheme suitable for lightweight applications. This paper presents an efficient hardware systolic accelerator for RBLWE-based PQC, targeting highperformance applications. We have briefly given the algorithmic background for the proposed design. Then, we have transferred the proposed algorithmic operation into a new systolic accelerator. Lastly, field-programmable gate array (FPGA) implementation results have confirmed the efficiency of the proposed accelerator.engbook parthttp://dx.doi.org/10.1109/CODES-ISSS55005.2022.00009https://ieeexplore.ieee.org/open access004.8Polynomial multiplicationPQCRBLWESystolic hardware acceleratorInteligencia artificial (Informática)1203.04 Inteligencia Artificial