Castro, F.Chaver Martínez, Daniel ÁngelPiñuel Moreno, LuisPrieto Matías, ManuelHuang, M. C.Tirado Fernández, José Francisco2023-06-202023-06-2020053-540-29013-3https://hdl.handle.net/20.500.14352/53421© Springer-Verlag Berlin Heidelberg 2005. We want to thank Simha Sethumadhavan for his helpful and thorough comments. International Workshop on Power and Timing Modeling, Optimization and Simulation (15th. sep 21-23, 2005.Lovaina, Belgica).The load-store queue (LQ-SQ) of modem superscalar processors is responsible for keeping the order of memory operations. As the performance gap between processing speed and memory access becomes worse, the capacity requirements for the LQ-SQ increase, and its design becomes a challenge due to its CAM structure. In this paper we propose an efficient load-store queue state filtering mechanism that provides a significant energy reduction (on average 35% in the LSQ and 3.5% in the whole processor), and only incurs a negligible performance loss of less than 0.6%.engbook parthttp://link.springer.com/chapter/10.1007/11556930_1http://link.springer.comhttp://www.ece.rochester.edu/~mihuang/PAPERS/patmos05.pdfopen access004Computer sciencehardware & architecturetheory & methodsEngineeringelectrical & electronicInformática (Informática)Programación de ordenadores (Informática)1203.17 Informática1203.23 Lenguajes de Programación