Imaña Pascual, José LuisPiñuel Moreno, LuisKuo, Yao-MingRuano Ramos, ÓscarGarcía Herrero, Francisco Miguel2024-10-212024-10-212024-08J. L. Imaña, L. Piñuel, Y. -M. Kuo, O. Ruano and F. García-Herrero, "Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, no. 8, pp. 3915-3919, Aug. 2024, doi: 10.1109/TCSII.2024.33691031549-774710.1109/TCSII.2024.3369103https://hdl.handle.net/20.500.14352/109186Binary extension field arithmetic is widely used in several important applications such as error-correcting codes, cryptography and digital signal processing. Multiplication is usually considered the most important finite field arithmetic operation. Therefore efficient hardware architectures for multiplication are highly desired. In this brief, a new architecture for multiplication over finite fields generated by irreducible trinomials f(x) = xm + xt + 1 is presented. The architecture here proposed is based on the use of a polynomial multiplier and a cyclic shift register that can perform the multiplication in t − 1 clock cycles. The general architecture is applied to the trinomials recommended by NIST (National Institute of Standards and Technology). Furthermore, a RISC-V instruction set for the proposed multiplier is implemented and validated using VeeR-EL2 on a Nexys A7 FPGA. To the best knowledge of the authors, this is the first work that integrates the multiplication based on NIST trinomials into a RISC-V SoC. Results show an improvement of several orders of magnitude in terms of latency at a cost of less than 50% more of area.engAttribution 4.0 Internationalhttp://creativecommons.org/licenses/by/4.0/journal article1558-3791https://doi.org/10.1109/TCSII.2024.3369103https://ieeexplore.ieee.org/document/10444058open access004004.056.55Error-correcting codesCryptographyFinite field arithmeticMultiplicationNIST trinomialsRISC-VHardware3304 Tecnología de Los Ordenadores