Acciarito, SimoneCardarilli, Gian CarloCristini, AlessandroDi Nunzio, LucaFazzolari, RoccoKhanal, Gaurav ManiRe, MarcoSusi, Gianluca2025-01-292025-01-292017-09Acciarito, S., Cardarilli, G.C., Cristini, A., Nunzio, L.D., Fazzolari, R., Khanal, G.M., Re, M., Susi, G., 2017. Hardware design of LIF with Latency neuron model with memristive STDP synapses. Integration 59, 81–89. https://doi.org/10.1016/j.vlsi.2017.05.0060720-512010.1016/j.vlsi.2017.05.006https://hdl.handle.net/20.500.14352/116839Se deposita la versión aceptada (postprint) del artículoIn this paper, the hardware implementation of a neuromorphic system is presented. This system is composed of a Leaky Integrate-and-Fire with Latency (LIFL) neuron and a Spike-Timing Dependent Plasticity (STDP) synapse. LIFL neuron model allows to encode more information than the common Integrate-and-Fire models, typically considered for neuromorphic implementations. In our system LIFL neuron is implemented using CMOS circuits while memristor is used for the implementation of the STDP synapse. A description of the entire circuit is provided. Finally, the capabilities of the proposed architecture have been evaluated by simulating a motif composed of three neurons and two synapses. The simulation results confirm the validity of the proposed system and its suitability for the design of more complex spiking neural networks.engjournal article2941-8895https://doi.org/10.1016/j.vlsi.2017.05.006https://www.sciencedirect.com/science/article/pii/S0167926017303206open access004.04860253Leaky Integrate-and-Fire with Latency (LIFL)NeuronSynapseSTDPMemristorNeuromorphic systemAnalog VLSIBioinformáticaInteligencia artificial (Informática)Informática médica y telemedicina3314 Tecnología Médica2404 Biomatemáticas3304.06 Arquitectura de Ordenadores