Imaña Pascual, José Luis2023-06-162023-06-162021-081549-774710.1109/TCSII.2021.3071188https://hdl.handle.net/20.500.14352/4479©2021 IEEE This work was supported by the Spanish MINECO and CM under Grant S2018/TCS-4423 and Grant RTI2018-093684-B-I00.Arithmetic operations over binary extension fields GF(2^m) have many important applications in domains such as cryptography, code theory and digital signal processing. These applications must be fast, so low-delay implementations of arithmetic circuits are required. Among GF(2^m) arithmetic operations, field multiplication is considered the most important one. For hardware implementation of multiplication over binary finite fields, irreducible trinomials and pentanomials are normally used. In this brief, low-delay FPGA-based implementations of bit-parallel GF(2^m) polynomial basis multipliers are presented, where a new multiplier based on irreducible trinomials is given. Several post-place and route implementation results in Xilinx Artix-7 FPGA for different GF(2^m) finite fields are reported. Experimental results show that the proposed multiplier exhibits the best delay, with a delay improvement of up to 4.7%, and the second best Area x Time complexities when compared with similar multipliers found in the literature.engjournal articlehttp://dx.doi.org/10.1109/TCSII.2021.3071188https://ieeexplore.ieee.org/open access004.8ParallelComplexityMultipliersBit-parallelGalois fieldsPolynomial basisTrinomialsInteligencia artificial (Informática)1203.04 Inteligencia Artificial