Imaña Pascual, José Luis2023-06-172023-06-172021-01-010018-934010.1109/TC.2020.2980259https://hdl.handle.net/20.500.14352/7669© 2021 Institute of Electrical and Electronics This work was supported in part by the Spanish MINECO and CM under Grant S2018/TCS-4423, Grant TIN 2015-65277-R, and Grant RTI2018-093684-B-I00.In this article, a new architecture of bit-serial polynomial basis (PB) multipliers over the binary extension field GF(^2m) generated by irreducible trinomials is presented. Bit-serial GF(^2m) PB multiplication offers a performance/area trade-off that is very useful in resource constrained applications. The architecture here proposed is based on LFSR (Linear-Feedback Shift Register) and can perform a multiplication in m clock cycles with a constant propagation delay of T_A + T_X. These values match the best time results found in the literature for bit-serial PB multipliers with a slight reduction of the space complexity. Furthermore, the proposed architecture can perform the multiplication of two operands for t different finite fields GF(^2m) generated by t irreducible trinomials simultaneously in m clock cycles with the inclusion of t(m - 1) flipflops and tm XOR gates.engjournal articlehttp://dx.doi.org/10.1109/TC.2020.2980259https://ieeexplore.ieee.orgopen access004.8MultiplicationArchitecturesMultipliersLFSRBit-serialGF(^2m)Polynomial basisTrinomialsInteligencia artificial (Informática)1203.04 Inteligencia Artificial