Clemente Barreira, Juan AntonioMansour, WassimAyoubi, RaficSerrano, FelipeMecha López, HortensiaZiade, HaissamEl Falou, WassimVelazco, Raoul2023-06-182023-06-182016-01-010925-2312http://0-dx.doi.org.cisne.sim.ucm.es/10.1016/j.neucom.2015.06.038https://hdl.handle.net/20.500.14352/24602This letter presents an FPGA implementation of a fault-tolerant Hopfield NeuralNetwork (HNN). The robustness of this circuit against Single Event Upsets (SEUs) and Single Event Transients (SETs) has been evaluated. Results show the fault tolerance of the proposed design, compared to a previous non fault- tolerant implementation and a solution based on triple modular redundancy (TMR) of a standard HNN design.engjournal articlehttp://0-www.sciencedirect.com.cisne.sim.ucm.es/science/article/pii/S0925231215008760open access004.032.26004.312004.052.3Artificial Neural Network (ANN)Hopfield Neural Network (HNN)Single Event Upset (SEU)Single Event Transient (SET)FPGAFault toleranceHardware