Chaver Martínez, Daniel ÁngelHarris, SarahPiñuel Moreno, LuisKindgren, OlofKakakhel, ZubairOwen, ChrisKravitz, RoyGómez Pérez, José IgnacioCastro Rodríguez, FernandoOlcoz Herrero, KatzalinVillalba Moreno, JulioGrinshpun, AlexanderGabbay, FredduSeed, LukeDuarte, RuiLópez, ManuelAlonso, ÓscarOwen, Robert2026-02-132026-02-132026-02-06D. Chaver et al., "The RISC-V FPGA (RVfpga) Teaching Package," in IEEE Access, vol. 14, pp. 18455-18475, 2026, doi: 10.1109/ACCESS.2026.3658743.10.1109/ACCESS.2026.3658743https://hdl.handle.net/20.500.14352/132377© 2026 The Authors.RISC-V is a free and open-standard ISA based on RISC principles, allowing anyone to design, manufacture, and sell RISC-V chips and software. Its flexibility and growing ecosystem have made it popular in research, education, and industry, increasing the need for educational materials. This paper provides an in-depth description of the RVfpga course, which offers a solid introduction to computer architecture using the RISC-V instruction set and FPGA technology. It focuses on providing hands-on experience with real-world RISC-V cores, the VeeR EH1 and EL2 cores, developed by Western Digital and hosted by ChipsAlliance. The course targets students and educators in computing-related fields, enabling them to integrate practical RISC-V knowledge into their curricula. The course materials, which include detailed labs, setup guides, and the full SoC source code in System Verilog, are available for free. Students learn to compile, debug, and run C and assembly programs, to interact with built-in peripherals, to extend the SoC, and to explore microarchitectural features.engAttribution-NonCommercial-NoDerivatives 4.0 Internationalhttp://creativecommons.org/licenses/by-nc-nd/4.0/journal article2169-3536https://dx.doi.org/10.1109/ACCESS.2026.3658743https://ieeexplore.ieee.org/document/11366652open access004.3Computer architectureComputer science educationEducation coursesMicroarchitectureHardware3304 Tecnología de Los Ordenadores